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<p>This paper presents a novel Filter Bank (FB) architecture for Two-Dimensional (2D) Finite Impulse Response (FIR) filters that leverage symmetric processing, parallelism, and Distributed Arithmetic (DA) to optimize the Design. The architecture employs parallel processing to enhance throughput by a factor of L, where L represents the parallel processing block length (block size). Exploiting symmetry in filter coefficients significantly reduces the number of required multipliers. The remaining multipliers are replaced with DA-based multipliers, where the standard DA approach is enhanced through a Dual-Port (DP) Look Up Table (LUT) design, allowing two simultaneous input accesses to the LUT, to further reduce area and power consumption. This DP LUT-based multiplication method is utilized to analyze and construct filter architectures for four different symmetric coefficient matrices. These architectures are integrated through a shared memory module and control logic, which selectively activates the required filter while disabling others, thereby minimizing power usage. The design is implemented in Verilog Hardware Description Language (HDL) and synthesized for a Field Programmable Gate Array (FPGA) using Xilinx tools. Subsequently, Cadence Genus synthesizes the design in 45&#xa0;nm CMOS technology for Application-Specific Integrated Circuit (ASIC) implementation. Comprehensive comparisons of area, delay, and power are presented across various 2D FIR filter architectures. Finally, the proposed design’s layout is evaluated using the Cadence Innovus tool for place and route, validating the efficiency of the architecture. The proposed filter architectures exploiting coefficient symmetry demonstrate significant improvements, with Area–Delay Product (ADP) reduced by 3.3–99.3% and Power–Delay Product (PDP) reduced by 6.3–82.4% compared to existing architectures.</p>

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Distributed arithmetic computation-based 2D FIR Filter Bank with parallel processing and symmetry concepts

  • 期刊论文

  • 发表日期：

    2025年9月23日

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  • Venkata Krishna Odugu,
  • Harish Babu Gade

摘要

This paper presents a novel Filter Bank (FB) architecture for Two-Dimensional (2D) Finite Impulse Response (FIR) filters that leverage symmetric processing, parallelism, and Distributed Arithmetic (DA) to optimize the Design. The architecture employs parallel processing to enhance throughput by a factor of L, where L represents the parallel processing block length (block size). Exploiting symmetry in filter coefficients significantly reduces the number of required multipliers. The remaining multipliers are replaced with DA-based multipliers, where the standard DA approach is enhanced through a Dual-Port (DP) Look Up Table (LUT) design, allowing two simultaneous input accesses to the LUT, to further reduce area and power consumption. This DP LUT-based multiplication method is utilized to analyze and construct filter architectures for four different symmetric coefficient matrices. These architectures are integrated through a shared memory module and control logic, which selectively activates the required filter while disabling others, thereby minimizing power usage. The design is implemented in Verilog Hardware Description Language (HDL) and synthesized for a Field Programmable Gate Array (FPGA) using Xilinx tools. Subsequently, Cadence Genus synthesizes the design in 45 nm CMOS technology for Application-Specific Integrated Circuit (ASIC) implementation. Comprehensive comparisons of area, delay, and power are presented across various 2D FIR filter architectures. Finally, the proposed design’s layout is evaluated using the Cadence Innovus tool for place and route, validating the efficiency of the architecture. The proposed filter architectures exploiting coefficient symmetry demonstrate significant improvements, with Area–Delay Product (ADP) reduced by 3.3–99.3% and Power–Delay Product (PDP) reduced by 6.3–82.4% compared to existing architectures.