Pragmatic analysis of polyphase CIC decimation filter for next generation wireless applications

This paper enunciates the polyphase segmentation of a non-recursive Cascaded Integrator Comb (CIC) decimation filter by employing different parallel prefix adders. Polyphase decomposition is an efficient method of performing sampling rate conversion which is suitable for software-defined radio applications. The innovative polyphase-based non-recursive CIC filter presents a distinctive architecture that delivers accelerated processing speeds and reduced power consumption when contrasted with recursive CIC filters. In this brief, the examination of the proposed non-recursive CIC and its polyphase architecture has been done on Kintex7 FPGA using Xilinx 14.7. Also, the magnitude response has been exemplified using MATLAB. In compliance with the output obtained on the Kintex 7 FPGA, the proposed non-recursive CIC filter, which employs a hybrid PPF CSL adder, surpasses the current recursive and non-recursive CIC counterparts by using additional parallel prefix adders, by virtue of power consumption as 38.05% and path delay as 57.34%. Similarly, the proposed polyphase multiplierless CIC filter using a hybrid PPF CSL adder achieves a 38.67% reduction in power consumption, a 60.41% decrease in path delay, and an 82.64% reduction in the number of required LUTs in contrast with the existing multiplierless filter. To enhance the magnitude characteristic of the proposed filter, a unique polynomial function has been derived which minimizes passband droop by 34.27% and stopband ripple by 73.41% in contrast with the existing filter.