Analysis of interface trap charges on RF/analog performances of dual-gate-source-drain Schottky FET for high-frequency applications

This article mainly focuses on the impact on interface trap charges (ITCs) on dual gate source-drain Schottky barrier tunnel field effect transistor (D-G-S-D-STFET) using a high-k dielectric material. Here the high-k material raises the coupling capacitance between the channel and the gate electrode, therefore increases the charge concentration more than a conventional device because of the additional dual-source region. A higher I_on/I_off current ratio and a reduced off-state leakage are obtained in the design of D-G-S-D-STFET. Moreover, the comparison of the D-G-S-D-STFET device is made with both the dual-metal gate TFET and conventional STFET. Further, the DC and analog/RF performances are characterized by Silvaco TCAD in terms of transfer characteristics (I_D–V_GS), cut-off frequency (f_T), transconductance (g_m), gain bandwidth product (GBP), transconductance generation factor (TGF), and transconductance frequency product (TFP). Comparatively to the conventional structures at a gate length of 40 nm has been observed that the Cut-off Frequency (f_T) and the TGF are increased in the proposed device to 60 GHz and 259 V⁻¹ range respectively with the positive and negative trap charges. Hence, the results verify that the D-G-S-D-STFET is more suitable for high-frequency applications.