Performance enhancement of junctionless silicon nanotube gate-all-around FETs for nano-scaled devices

This paper presents a novel structure of TSV-based silicon nanotube gate-all-around FETs (both junction-based and junctionless) along with their electrical characteristics using Silvaco ATLAS 3D device simulator. In comparison, the junctionless silicon nanotube gate-all-around structures presented an excellent performance improvement over the junction-based structures in terms of short channel effects, an improved drain-induced barrier lowering of ~ 28% for n-MOS and ~ 22% for p-MOS, and improved (I_ON/I_OFF) switching ratio of ~ 68% for n-MOS and ~ 42% for p-MOS. Similarly, the junctionless structure shows a steep subthreshold value very close to the ideal value (~ 60 mv/dec). Furthermore, the static and transient characteristics of CMOS inverter circuits designed using the complementary device architecture have been explored using mixed-mode simulations. The noise margin and propagation delay of the circuit are analyzed and are found to agree with the information available in the literature for nano-scaled devices.