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<p>The given paper introduces a novel approach which involves the design and implementation of a UART (Universal Asynchronous Receiver/Transmitter) module with FIFO (First-In-First-Out) buffering, developed using Verilog HDL and verified on a Basys 3 FPGA board through Xilinx Vivado 2023.2.) UART is a standard serial communication interface used in embedded systems for reliable data exchange. FIFO integration enhances serial data flow by reducing CPU overhead and improving full-duplex performance. In addition to functional implementation, this paper identifies the research gap between existing FIFO-based UART designs, particularly focusing on earlier works that lacked hardware buffering or efficient timing strategies. The study identifies which FPGA platforms are suitable for low-power, high-performance UART applications, and highlights improvements over earlier FPGA generations. The results demonstrate that the system meets its performance targets in terms of timing, power, and resource utilization, while the simulation waveforms validate the correct functional operation of both transmitter and receiver modules.</p>

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A novel approach to ensure efficient asynchronous communication using FIFO-based UART module

  • 期刊论文

  • 发表日期：

    2025年12月24日

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  • Avinash A. B. Roy,
  • A. Ambikapathy,
  • Setu Garg,
  • R. Anand,
  • Aditya Dayal Tyagi,
  • Akmal Hussain,
  • S. Junith Ahmed

摘要

The given paper introduces a novel approach which involves the design and implementation of a UART (Universal Asynchronous Receiver/Transmitter) module with FIFO (First-In-First-Out) buffering, developed using Verilog HDL and verified on a Basys 3 FPGA board through Xilinx Vivado 2023.2.) UART is a standard serial communication interface used in embedded systems for reliable data exchange. FIFO integration enhances serial data flow by reducing CPU overhead and improving full-duplex performance. In addition to functional implementation, this paper identifies the research gap between existing FIFO-based UART designs, particularly focusing on earlier works that lacked hardware buffering or efficient timing strategies. The study identifies which FPGA platforms are suitable for low-power, high-performance UART applications, and highlights improvements over earlier FPGA generations. The results demonstrate that the system meets its performance targets in terms of timing, power, and resource utilization, while the simulation waveforms validate the correct functional operation of both transmitter and receiver modules.