Scholarlink

<p>On-chip decoupling capacitors (decaps) are critical for managing power supply noise, particularly in addressing simultaneous switching current demands. However, their inclusion often results in increased area consumption and leakage power. Traditionally, decaps must be placed close to current loads to ensure reliable circuit operation, which imposes significant design constraints. This work introduces a novel methodology to reduce the number of on-chip decaps by reconfiguring unused spare cells within the design. A custom “Free Placement” strategy enables seamless and highly efficient integration of these reconfigured decaps into semicustom digital designs. Unlike conventional approaches, this methodology eliminates the need for physically placing decaps near high current loads offering enhanced design flexibility and spatial efficiency. Comparative studies demonstrate that this technique significantly outperforms traditional methods, achieving notable reductions in both effective usable area and total leakage current. The spare cells reconfigured as decaps combined with the “Free Placement” methodology, reduces both design cycle time and implementation effort.</p>

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A smart “Free Placement” methodology for novel “Spare-cell reconfigured as Decoupling Capacitors” in standard-cell based digital ASICs

  • 期刊论文

  • 发表日期：

    2025年12月19日

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  • K. Ranjit Kannan,
  • G. Lakshmi Narayanan

摘要

On-chip decoupling capacitors (decaps) are critical for managing power supply noise, particularly in addressing simultaneous switching current demands. However, their inclusion often results in increased area consumption and leakage power. Traditionally, decaps must be placed close to current loads to ensure reliable circuit operation, which imposes significant design constraints. This work introduces a novel methodology to reduce the number of on-chip decaps by reconfiguring unused spare cells within the design. A custom “Free Placement” strategy enables seamless and highly efficient integration of these reconfigured decaps into semicustom digital designs. Unlike conventional approaches, this methodology eliminates the need for physically placing decaps near high current loads offering enhanced design flexibility and spatial efficiency. Comparative studies demonstrate that this technique significantly outperforms traditional methods, achieving notable reductions in both effective usable area and total leakage current. The spare cells reconfigured as decaps combined with the “Free Placement” methodology, reduces both design cycle time and implementation effort.