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<p>Hardware intellectual property protection presents significant challenges in modern semiconductor design. This paper introduces a novel watermarking technique embedded during high-level synthesis register allocation. The methodology integrates a unique signature as the watermark without compromising functionality, performance, or area utilisation. A distinctive verification strategy enables end-users to independently authenticate the watermark without designer involvement. The approach employs satisfiability-based optimisation and graph colouring to minimise register usage, yielding negligible area overhead. Experimental validation confirms the technique’s effectiveness in securing designs while maintaining minimal resource impact. The verification mechanism utilises a hash digest for secure ownership confirmation, enhancing IP protection throughout the design lifecycle.</p>

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Hardware IP watermarking and verification strategy in high level synthesis

  • 期刊论文

  • 发表日期：

    2025年10月9日

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  • C. S. Ashwin,
  • Suchismita Roy

摘要

Hardware intellectual property protection presents significant challenges in modern semiconductor design. This paper introduces a novel watermarking technique embedded during high-level synthesis register allocation. The methodology integrates a unique signature as the watermark without compromising functionality, performance, or area utilisation. A distinctive verification strategy enables end-users to independently authenticate the watermark without designer involvement. The approach employs satisfiability-based optimisation and graph colouring to minimise register usage, yielding negligible area overhead. Experimental validation confirms the technique’s effectiveness in securing designs while maintaining minimal resource impact. The verification mechanism utilises a hash digest for secure ownership confirmation, enhancing IP protection throughout the design lifecycle.