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<p>This paper presents a novel architecture of three stage ring VCO implemented using gpdk 90&#xa0;nm technology for low power, compact sized portable devices for communication systems. In this design, CMOS based NOR gate delay stage using pull-up and pull-down transistors is introduced to minimize the power consumption. The simulation results of the proposed VCO shows that it achieves 7.3&#xa0;GHz at 1&#xa0;V supply voltage with an average power consumption of 0.532µW. The obtained phase noise and FOM are − 71.91dBc/Hz @1&#xa0;MHz and − 211.91 @ 7.3&#xa0;GHz respectively. The proposed design occupies a total area of (12 × 13.1) µm<sup>2</sup>. The presented design is analyzed with different process corners and temperatures to verify the robustness of the VCO design.</p>

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An ultra low power VCO design using NOR gate delay stage

  • 期刊论文

  • 发表日期：

    2025年7月2日

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  • Isha Kadyan,
  • Manoj Kumar,
  • Amit Prakash Singh

摘要

This paper presents a novel architecture of three stage ring VCO implemented using gpdk 90 nm technology for low power, compact sized portable devices for communication systems. In this design, CMOS based NOR gate delay stage using pull-up and pull-down transistors is introduced to minimize the power consumption. The simulation results of the proposed VCO shows that it achieves 7.3 GHz at 1 V supply voltage with an average power consumption of 0.532µW. The obtained phase noise and FOM are − 71.91dBc/Hz @1 MHz and − 211.91 @ 7.3 GHz respectively. The proposed design occupies a total area of (12 × 13.1) µm2. The presented design is analyzed with different process corners and temperatures to verify the robustness of the VCO design.