Novel hardware architectures of improved-LEA lightweight cipher for IoT applications

The Internet of Things (IoTs), smart cards, and other ubiquitous computing devices have grown exponentially since last decade. These devices demand new security and protection concerns. Lightweight cryptography presents security requirements suitable for constraint conditions. The paper introduces an efficient hardware architectures of an LEA (Lightweight Encryption Algorithm) lightweight block cipher for low-resource IoTs applications. An improved 128-bit key round design with good throughput and area optimization is proposed for the Improved-LEA cipher. Moreover, a full description of a 128-bit key pipelined and 192-bit key pipelined high-throughput architecture for the Improved-LEA cipher is proposed. The implementation results of those proposed architectures are carried out by using different FPGA platforms in terms of number of Look-up Tables (LUTs), maximum operating frequency and throughput. These implemented results are compared with of existing architectures to ensure that the new design outperformed the earlier designs.