Low-power, high-speed comparator design at 45-nm CMOS for efficient deep learning acceleration

This paper explores optimizing a dynamic bias latch comparator for deep learning accelerators in computer vision. We investigate clock gating, cross-coupled transistors, and a novel hybrid approach, all simulated in 45nm Complementary Metal-Oxide-Semiconductor (CMOS) with LTspice. The hybrid design surpasses individual techniques, achieving a 24.89% and 13.25% reduction in power-delay product, respectively. Compared to the original design, it offers a 46.79% decrease at 1.2V. The optimized comparator design can be integrated into hardware accelerators for deep learning models, such as custom integrated circuits or Field Programmable Gate Array (FPGA)-based solutions, to enhance their efficiency and speed in processing computer vision tasks by reducing propagation delay and energy consumption.