A novel single-ended 9T SRAM cell with write assist and decoupled read path for efficient low-voltage applications

In this work, a novel single ended single port Write Assist Read decoupled (WARD) 9T SRAM bitcell is proposed to enhance improved write latency. The design incorporates a low threshold (V_TH) write access transistor and leverages virtual ground (VGND) assist for low voltage operation at 32 nm CMOS technology node. It demonstrates notable improvements in write delay over conventional SRAM bitcells. At V_DD = 0.6 V, the WARD 9T cell offers reduced write’1’ delay and write’0’ delay. Additionally, WARD 9T cell demonstrates a substantial reduction in read delay and bitline leakage attributed to the stacked configuration for n-type transistors.