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<p>We present a protected hardware implementation of the Module-Lattice-Based Digital Signature Standard (ML-DSA). ML-DSA is an extension of Dilithium 3.1, which is the winner of the Post Quantum Cryptography (PQC) competition in the digital signature category. The proposed design is based on the existing high-performance Dilithium 3.1 design. We implemented existing Dilithium masking gadgets in hardware, which were only implemented in software. The masking gadgets are integrated with the unprotected ML-DSA design, and functional verification of the complete design is verified using the Known Answer Tests(KATs) generated from ML-DSA reference software. We also present the practical power side-channel attack experimental results by implementing masking gadgets on the standard side-channel evaluation FPGA board and collecting power traces of up to 1 million. The proposed protected design has the overhead of 1.127<InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(\times \)</EquationSource> </InlineEquation> LUT, 1.2<InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(\times \)</EquationSource> </InlineEquation> Flip-Flop, and 378<InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(\times \)</EquationSource> </InlineEquation> execution time compared to the unprotected design. The experimental results show that it resists side-channel attacks.</p>

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Improved ML-DSA Hardware Implementation with First Order Masking Countermeasure

  • 期刊论文

  • 发表日期：

    2026年6月1日

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  • Kamal Raj,
  • Prasanna Ravi,
  • Tee Kiah Chia,
  • Anupam Chattopadhyay

摘要

We present a protected hardware implementation of the Module-Lattice-Based Digital Signature Standard (ML-DSA). ML-DSA is an extension of Dilithium 3.1, which is the winner of the Post Quantum Cryptography (PQC) competition in the digital signature category. The proposed design is based on the existing high-performance Dilithium 3.1 design. We implemented existing Dilithium masking gadgets in hardware, which were only implemented in software. The masking gadgets are integrated with the unprotected ML-DSA design, and functional verification of the complete design is verified using the Known Answer Tests(KATs) generated from ML-DSA reference software. We also present the practical power side-channel attack experimental results by implementing masking gadgets on the standard side-channel evaluation FPGA board and collecting power traces of up to 1 million. The proposed protected design has the overhead of 1.127 \(\times \) LUT, 1.2 \(\times \) Flip-Flop, and 378 \(\times \) execution time compared to the unprotected design. The experimental results show that it resists side-channel attacks.