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<p>The proliferation of the Internet of Things (IoT) devices has increased security concerns, as these devices suffer from limited computational resources, restricting traditional encryption methods. Physically unclonable functions (PUFs) provide a lightweight and cost-effective alternative for secure authentication. This study presents an optimized resistor–capacitor (RC) PUF design for IoT security, focusing on the effects of input time delay and output bit selection on an analog-to-digital (ADC) converter for enhanced performance. We evaluate first-order (RC1) and second-order (RC2) PUF architectures, optimizing resistance (<i>R</i>), capacitance (<i>C</i>), bit delays, and ADC bit selection to improve uniqueness, uniformity, reliability, and bit aliasing. Experimental results indicate that the 5th ADC bit out of 12 bits provides optimal performance, balancing uniqueness (~ 50%), reliability (&gt; 90%), and minimal bit aliasing (~ 50%). Additionally, incorporating an XOR-based challenge with the microcontroller’s unique identity (ID) improves uniqueness. The National Institute of Standards and Technology (NIST) SP 800–22 randomness tests confirm strong unpredictability (95–98%), making the proposed RC PUF highly suitable for secure IoT authentication. The design’s simplicity and low-cost implementation ensure seamless integration of our proposed PUF into existing IoT ecosystems.</p>

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Optimized RC-PUF Design for IoT Security: Evaluation of the Impact of ADC Bit Selection and Time Delay on Uniqueness, Reliability, and Statistical Randomness

  • 期刊论文

  • 发表日期：

    2025年10月2日

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  • Joy Acharya,
  • Paawan Sharma,
  • Mohendra Roy

摘要

The proliferation of the Internet of Things (IoT) devices has increased security concerns, as these devices suffer from limited computational resources, restricting traditional encryption methods. Physically unclonable functions (PUFs) provide a lightweight and cost-effective alternative for secure authentication. This study presents an optimized resistor–capacitor (RC) PUF design for IoT security, focusing on the effects of input time delay and output bit selection on an analog-to-digital (ADC) converter for enhanced performance. We evaluate first-order (RC1) and second-order (RC2) PUF architectures, optimizing resistance (R), capacitance (C), bit delays, and ADC bit selection to improve uniqueness, uniformity, reliability, and bit aliasing. Experimental results indicate that the 5th ADC bit out of 12 bits provides optimal performance, balancing uniqueness (~ 50%), reliability (> 90%), and minimal bit aliasing (~ 50%). Additionally, incorporating an XOR-based challenge with the microcontroller’s unique identity (ID) improves uniqueness. The National Institute of Standards and Technology (NIST) SP 800–22 randomness tests confirm strong unpredictability (95–98%), making the proposed RC PUF highly suitable for secure IoT authentication. The design’s simplicity and low-cost implementation ensure seamless integration of our proposed PUF into existing IoT ecosystems.