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Background <p>The high-energy underwater neutrino telescope, proposed by the Institute of High Energy Physics of the Chinese Academy of Sciences, aims to detect ultra-high-energy neutrinos exceeding 100&#xa0;TeV by deploying a 30&#xa0;km<sup>3</sup> detector array in a deep-sea environment. The use of 20-inch photomultiplier tubes (PMTs) in this massive array necessitates the frontend readout electronics system capable of performing real-time processing and long-distance transmission.</p> Purpose <p>With a sampling rate of 1&#xa0;Gsps and an average background counting rate per PMT channel of 60&#xa0;kHz, the frontend readout electronics system generates a raw data bandwidth of approximately 2.9&#xa0;Gbps per board. To alleviate the long-distance transmission burden of waveform data selected by the global trigger based on arrival time (<i>T</i>) and charge (<i>Q</i>) information, and to conserve on-board storage resources, this paper presents an efficient lossless data-compression architecture implemented within the frontend FPGA.</p> Methods <p>This paper proposes an FPGA-based heterogeneous lossless compression architecture. For trigger data streams with stringent real-time requirements, a dynamic coarse–fine timestamp remapping strategy is developed for arrival time (<i>T</i>), coupled with a physical threshold-based range saturation strategy for charge (<i>Q</i>). For waveform data (<i>W</i>) intended for offline analysis, a hybrid compression strategy integrating Bitshuffle preprocessing with Zstd customized using pretrained static FSE tables is designed to exploit baseline-dominated waveforms containing sparse pulses.</p> Results <p>The dynamic remapping algorithm for timing information achieves a 3.24× compression ratio under an 18-bit fine timestamp configuration. Simultaneously, the range saturation strategy for charge information attains a 1.5× compression ratio without compromising the integrity of the trigger logic. For waveform data, the hardware-accelerated algorithm implemented on the Xilinx Kintex-7 FPGA realizes a 2.99× compression ratio and a throughput of 1&#xa0;GB/s at a 250&#xa0;MHz clock frequency, ensuring lossless reconstruction. Ultimately, the proposed scheme reduces the data bandwidth requirement to within the capacity of the existing transmission links.</p>

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An FPGA-based lossless data-compression scheme for high-energy underwater neutrino telescope (HUNT)

  • 期刊论文

  • 发表日期：

    2026年5月27日

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  • Liang-kun Zhang,
  • Jin-fan Chang,
  • Feng-fan Yang,
  • Xing Zhou

摘要

Background

The high-energy underwater neutrino telescope, proposed by the Institute of High Energy Physics of the Chinese Academy of Sciences, aims to detect ultra-high-energy neutrinos exceeding 100 TeV by deploying a 30 km3 detector array in a deep-sea environment. The use of 20-inch photomultiplier tubes (PMTs) in this massive array necessitates the frontend readout electronics system capable of performing real-time processing and long-distance transmission.

Purpose

With a sampling rate of 1 Gsps and an average background counting rate per PMT channel of 60 kHz, the frontend readout electronics system generates a raw data bandwidth of approximately 2.9 Gbps per board. To alleviate the long-distance transmission burden of waveform data selected by the global trigger based on arrival time (T) and charge (Q) information, and to conserve on-board storage resources, this paper presents an efficient lossless data-compression architecture implemented within the frontend FPGA.

Methods

This paper proposes an FPGA-based heterogeneous lossless compression architecture. For trigger data streams with stringent real-time requirements, a dynamic coarse–fine timestamp remapping strategy is developed for arrival time (T), coupled with a physical threshold-based range saturation strategy for charge (Q). For waveform data (W) intended for offline analysis, a hybrid compression strategy integrating Bitshuffle preprocessing with Zstd customized using pretrained static FSE tables is designed to exploit baseline-dominated waveforms containing sparse pulses.

Results

The dynamic remapping algorithm for timing information achieves a 3.24× compression ratio under an 18-bit fine timestamp configuration. Simultaneously, the range saturation strategy for charge information attains a 1.5× compression ratio without compromising the integrity of the trigger logic. For waveform data, the hardware-accelerated algorithm implemented on the Xilinx Kintex-7 FPGA realizes a 2.99× compression ratio and a throughput of 1 GB/s at a 250 MHz clock frequency, ensuring lossless reconstruction. Ultimately, the proposed scheme reduces the data bandwidth requirement to within the capacity of the existing transmission links.