Design of a wafer-scale ultra-thin silicon pixel detector prototype

In the upgrade study of the BESIII inner drift chamber, a two-layer concentric cylindrical silicon pixel detector is proposed, which will be positioned between the beam pipe and the inner drift chamber.

The detector consists of CMOS pixel sensors at wafer scale using chip stitching technology. The chips are thinned to a flexible thickness of about 50  \(\upmu \) $\mathrm{\mu }$ m. PMI foams are used as spacers and auxiliary support between the adjacent layers, enabling the first layer of the detector to be put as close to the central beam pipe as possible. The detector structure has been optimized through finite-element analysis (FEA).

The material budget of the detector has been reduced to about \({0.077}\%\) $0.077\%$ \(X_{0}\) $X_0$ per layer. The maximum deformation of the chip edge has been controlled to ± 80  \(\upmu \) $\mathrm{\mu }$ m after bending, and the roundness is about 100  \(\upmu \) $\mathrm{\mu }$ m, which verifies the feasibility of the cylindrical detector prototype structure. In addition, the wire bonding process for the cylindrical silicon pixel detector has been tested and preliminarily validated.

This study validates the process flow for the development of large-area cylindrical detectors based on stitching technology, laying a foundation for the smooth progress of subsequent study.