Design and Implementation of High-Speed Ternary Multiplier using New Family of Universal Ternary Logic Gates
摘要
One of the primary challenges in modern chip design is managing the extensive interconnections between digital logic blocks, which contribute significantly to power dissipation and chip area. Multi-valued logic (MVL), particularly ternary logic, offers a promising approach to reducing these interconnections, thereby enhancing the overall efficiency. This paper proposes a new family of universal ternary logic gates and the design of a ternary multiplier. The working of proposed circuits is based on voltage averaging technique, which is responsible for improving their power delay product (PDP). These circuits have been designed and simulated using Cadence Virtuoso tool with a standard 32 nm Stanford CNTFET model. The simulation results show that the proposed standard ternary inverter, standard ternary NAND, standard ternary NOR and 1-bit ternary multiplier exhibit PDP values of 0.25 × 10–19 J, 0.051 × 10–19 J, 0.15 × 10–19 J, and 1.239 × 10–18 J, respectively. The PDP of the proposed circuits is found to be superior to the existing architectures. Furthermore, a comprehensive parametric analysis is carried out to verify the robustness of the proposed ternary logic gates. The proposed ternary circuits reported in this work are expected to improve the performance of the ternary arithmetic and logical units used in neuromorphic computing.