<p>CMOS technology is approaching the limits of its developmental potential, prompting the exploration of alternative technologies to succeed it. Quantum-dot Cellular Automata (QCA) stands out as a viable future technology because of its ability to operate at terahertz frequencies, achieve high device density, and consume minimal power. Leading Zero Counters (LZCs) are fundamental components in a wide range of applications, including floating-point arithmetic normalization, data sketching, high-performance computing (HPC), data compression, cryptography, and parallel processing. Despite their importance, there appears no previous research which reported design and implementation of LZC in QCA framework. In this paper, we present novel design of a Leading Zero Counter using QCA to address this research gap. The design begins with a 2-bit LZC as the basic building block. By integrating two 2-bit LZCs, a 4-bit LZC is constructed. Following a similar hierarchical approach, two 4-bit LZCs are then integrated to form an 8-bit LZC. The QCADesigner 2.0.3 was utilized to design and simulate the proposed QCA designs to verify their logical correctness and functionality. A detailed evaluation of performance indicators such as cell count, area, latency, and cost has been carried out to assess the overall efficiency of the proposed architecture. Additionally, energy dissipation was assessed through simulations in the QCADesigner-E environment.</p>