Scholarlink

<p>The goal of this paper is to analyze, design, and simulate a homo/hetero structure tunnel field-effect transistor (TFET)-based dynamic comparator, which operates at very low voltage, very low power, and very high speed in a 65&#xa0;nm technology. The proposed design offers a promising solution for efficient and high-performance low-power comparator design in digital applications. Through extensive simulation and analysis, the effectiveness of the proposed design is demonstrated and compared with existing designs. This study provides valuable insights for the development of high-performance, low-power comparator design in the semiconductor industry. In this paper, we present a design and simulation of a MOSFET-based dynamic comparator with improved performance in TSMC 65&#xa0;nm technology. The post-layout simulation is implemented in the TSMC 65&#xa0;nm model and validated with Design Rule Check (DRC), Layout Versus Schematic (LVS), and Parasitic Extraction (PEX) tests to ensure the reliability and robustness of the simulation results. The time domain analysis of the post-layout simulation is also provided, which shows the circuit’s reliable performance. Finally, a homo/hetero-structure CTFET model with 65&#xa0;nm technology is created using the III-V model, and the proposed MOSFET-based dynamic comparator is compared with the CTFET model. To provide CMOS an opportunity to compare with CTFET, a model CTFET is developed using 65&#xa0;nm technology. Hence, the highest sampling frequency of 25 GS/s in PDP of 0.4325 fJ has been achieved in this article. The simulation results indicate that the proposed design has improved performance in terms of speed, power consumption, and stability.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Analysis of III-V Tunnel FET Homo/Hetero Structure Capabilities in 65 nm Technology

  • 期刊论文

  • 发表日期：

    2025年9月27日

查看全文
  • Mohsen DashtBayazi,
  • Seyed Ebrahim Hosseini,
  • Ehsan Naeemi

摘要

The goal of this paper is to analyze, design, and simulate a homo/hetero structure tunnel field-effect transistor (TFET)-based dynamic comparator, which operates at very low voltage, very low power, and very high speed in a 65 nm technology. The proposed design offers a promising solution for efficient and high-performance low-power comparator design in digital applications. Through extensive simulation and analysis, the effectiveness of the proposed design is demonstrated and compared with existing designs. This study provides valuable insights for the development of high-performance, low-power comparator design in the semiconductor industry. In this paper, we present a design and simulation of a MOSFET-based dynamic comparator with improved performance in TSMC 65 nm technology. The post-layout simulation is implemented in the TSMC 65 nm model and validated with Design Rule Check (DRC), Layout Versus Schematic (LVS), and Parasitic Extraction (PEX) tests to ensure the reliability and robustness of the simulation results. The time domain analysis of the post-layout simulation is also provided, which shows the circuit’s reliable performance. Finally, a homo/hetero-structure CTFET model with 65 nm technology is created using the III-V model, and the proposed MOSFET-based dynamic comparator is compared with the CTFET model. To provide CMOS an opportunity to compare with CTFET, a model CTFET is developed using 65 nm technology. Hence, the highest sampling frequency of 25 GS/s in PDP of 0.4325 fJ has been achieved in this article. The simulation results indicate that the proposed design has improved performance in terms of speed, power consumption, and stability.