<p>Due to rapid growth of portable electronic devices and the limitations of their internal batteries, design of low-power and energy-efficient VLSI circuits and systems is becoming more challenging in the field of electronic engineering. One of the aspects that can help towards reduction of power and energy dissipation of hardware components is to size individual transistors properly. In recent years, metaheuristic algorithms (MAs) have attracted many attentions for optimization of science and engineering problems. In this paper, transistor sizing optimization of digital circuits based on MAs is examined. For this purpose, full adder cell as a basic digital circuit is considered and sizing optimization is performed on four different topologies of this cell. Simulation results in TSMC-90&#xa0;nm CMOS process technology show that usage of some of the newest MAs such as American Zebra Optimization Algorithm, Dung Beetle Optimizer, Enhanced Snake Optimizer and Genghis Khan Shark Optimizer in transistor sizing can achieve the optimum value for full adder’s power-delay product better than older methods like particle swarm optimization and some of the other sizing algorithms presented before. However, some of the latest MAs are not successful for sizing optimization in comparison with their counterparts.</p>