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<p>Recently, there has been more demand for energy-saving computing solutions because of the increase in portable devices and Internet of Things (IoT) applications. The Full Adder (FA), a fundamental building block, plays a crucial role in many computational architectures. Emerging approaches, such as the Gate Diffusion Input (GDI) technique, have gained popularity for implementing FA designs due to their potential to reduce power consumption and transistor count. In the current work, a novel 10T GDI FA is proposed using the GDI technique with strategic bias voltage and the use of Low Voltage Threshold PMOS transistors. This work aims to improve performance, energy efficiency, and the output swing for Carry (Ca) and SUM (S). To validate the FA designs, post-layout functional simulations of different FA designs are verified using Cadence software at the 45&#xa0;nm Metal-Oxide-Semiconductor technology process. The results are then compared in terms of power, delay, power-delay product, and area. Monte Carlo and Process Corner simulations are also performed on both conventional and proposed FA designs. Finally, the simulation results show that the energy consumption of the proposed 10T GDI FA decreased by 37.04% compared to the conventional 10T GDI FA. Thus, the proposed FA circuit is suitable for applications requiring high performance and low power and can be embedded into energy-efficient systems.</p>

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A Modified GDI Full Adder Design for Enhanced Energy Efficiency

  • 期刊论文

  • 发表日期：

    2025年2月26日

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  • S. V. V. Satyanarayana,
  • B. Murali Krishna,
  • M. Thamarai,
  • D. Venkanna Babu,
  • S. Sudheer Reddy,
  • K. Baboji

摘要

Recently, there has been more demand for energy-saving computing solutions because of the increase in portable devices and Internet of Things (IoT) applications. The Full Adder (FA), a fundamental building block, plays a crucial role in many computational architectures. Emerging approaches, such as the Gate Diffusion Input (GDI) technique, have gained popularity for implementing FA designs due to their potential to reduce power consumption and transistor count. In the current work, a novel 10T GDI FA is proposed using the GDI technique with strategic bias voltage and the use of Low Voltage Threshold PMOS transistors. This work aims to improve performance, energy efficiency, and the output swing for Carry (Ca) and SUM (S). To validate the FA designs, post-layout functional simulations of different FA designs are verified using Cadence software at the 45 nm Metal-Oxide-Semiconductor technology process. The results are then compared in terms of power, delay, power-delay product, and area. Monte Carlo and Process Corner simulations are also performed on both conventional and proposed FA designs. Finally, the simulation results show that the energy consumption of the proposed 10T GDI FA decreased by 37.04% compared to the conventional 10T GDI FA. Thus, the proposed FA circuit is suitable for applications requiring high performance and low power and can be embedded into energy-efficient systems.