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<p>Gate-all-around field-effect transistors (GAA-FETs) represent the leading-edge channel architecture for constructing state-of-the-art high-performance FETs. Despite the advantages offered by the GAA configuration, its application to catalytic silicon nanowire (SiNW) channels, known for facile low-temperature fabrication and high yield, has faced challenges primarily due to issues with precise positioning and alignment. In exploring this promising avenue, we employed an in-plane solid–liquid-solid (IPSLS) growth technique to batch-fabricate orderly arrays of ultrathin SiNWs, with diameters of <i>D</i><sub>NW</sub> = 22.4 ± 2.4&#xa0;nm and interwire spacing of 90&#xa0;nm. An in situ channel-releasing technique has been developed to well preserve the geometry integrity of suspended SiNW arrays. By optimizing the source/drain contacts, high-performance GAA-FET devices have been successfully fabricated, based on these catalytic SiNW channels for the first time, yielding a high on/off current ratio of 10<sup>7</sup> and a steep subthreshold swing of 66&#xa0;mV&#xa0;dec<sup>−1</sup>, closing the performance gap between the catalytic SiNW-FETs and state-of-the-art GAA-FETs fabricated by using advanced top-down EBL and EUV lithography. These results indicate that catalytic IPSLS SiNWs can also serve as the ideal 1D channels for scalable fabrication of high-performance GAA-FETs, well suited for monolithic 3D integrations.</p>

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High-Performance Gate-All-Around Field Effect Transistors Based on Orderly Arrays of Catalytic Si Nanowire Channels

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年2月19日

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  • Wei Liao,
  • Wentao Qian,
  • Junyang An,
  • Lei Liang,
  • Zhiyan Hu,
  • Junzhuan Wang,
  • Linwei Yu

摘要

Gate-all-around field-effect transistors (GAA-FETs) represent the leading-edge channel architecture for constructing state-of-the-art high-performance FETs. Despite the advantages offered by the GAA configuration, its application to catalytic silicon nanowire (SiNW) channels, known for facile low-temperature fabrication and high yield, has faced challenges primarily due to issues with precise positioning and alignment. In exploring this promising avenue, we employed an in-plane solid–liquid-solid (IPSLS) growth technique to batch-fabricate orderly arrays of ultrathin SiNWs, with diameters of DNW = 22.4 ± 2.4 nm and interwire spacing of 90 nm. An in situ channel-releasing technique has been developed to well preserve the geometry integrity of suspended SiNW arrays. By optimizing the source/drain contacts, high-performance GAA-FET devices have been successfully fabricated, based on these catalytic SiNW channels for the first time, yielding a high on/off current ratio of 107 and a steep subthreshold swing of 66 mV dec−1, closing the performance gap between the catalytic SiNW-FETs and state-of-the-art GAA-FETs fabricated by using advanced top-down EBL and EUV lithography. These results indicate that catalytic IPSLS SiNWs can also serve as the ideal 1D channels for scalable fabrication of high-performance GAA-FETs, well suited for monolithic 3D integrations.