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<p>Human activity recognition (HAR) has notable applications in the health-care domains, such as in monitoring of the daily activities of elderly people to prevent accidents, assisting medical personnel in tracking rehabilitation progress, and enhancing therapeutic outcomes. In this study, we developed a convolutional recurrent fuzzy neural network (CRFNN) model for HAR. Convolutional and recurrent architectures are integrated with fuzzy logic in this model to ensure its ability to capture spatial and temporal features and handle ambiguous and uncertain data. The developed CRFNN model was deployed on a field-programmable gate array, on which the model achieved low power consumption, low latency, and efficient parallel computation, thus meeting the requirements for embedded applications. The developed model achieved a 4.8-times higher inference speed and 11.17-times lower energy consumption on the aforementioned array than on a graphics processing unit. Moreover, this model exhibited accuracy of 95.05% and 97.91% on the UCI-HAR and WISDM public datasets, respectively, indicating its effectiveness and practicality.</p>

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Implementation of a Convolutional Recurrent Fuzzy Neural Network Model on a High-Performance Field-Programmable Gate Array Accelerator for Real-Time Human Activity Recognition

  • 期刊论文

  • 发表日期：

    2025年8月12日

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  • Xue-Qian Lin,
  • Cheng-Jian Lin,
  • Jyun-Yu Jhang,
  • Sheng-Fu Liang

摘要

Human activity recognition (HAR) has notable applications in the health-care domains, such as in monitoring of the daily activities of elderly people to prevent accidents, assisting medical personnel in tracking rehabilitation progress, and enhancing therapeutic outcomes. In this study, we developed a convolutional recurrent fuzzy neural network (CRFNN) model for HAR. Convolutional and recurrent architectures are integrated with fuzzy logic in this model to ensure its ability to capture spatial and temporal features and handle ambiguous and uncertain data. The developed CRFNN model was deployed on a field-programmable gate array, on which the model achieved low power consumption, low latency, and efficient parallel computation, thus meeting the requirements for embedded applications. The developed model achieved a 4.8-times higher inference speed and 11.17-times lower energy consumption on the aforementioned array than on a graphics processing unit. Moreover, this model exhibited accuracy of 95.05% and 97.91% on the UCI-HAR and WISDM public datasets, respectively, indicating its effectiveness and practicality.