<p>Automated schematic layout for printed circuit boards (PCBs) is a critical step for security applications such as hardware Trojan detection and intellectual property verification. To address the challenges of state action space explosion and low training efficiency in reinforcement learning (RL) for PCB layout, posed by long decision sequences, this paper proposes a Segmented Reinforcement Learning (SRL) framework. SRL decouples long decision chains into sequential independent segments. Within each segment, separate segment agents optimize local policies, reducing state action space complexity while significantly improving training efficiency. Furthermore, segment agents achieve global coordination through cascaded propagation of optimal states, allowing SRL to avoid complex policy synchronization, which provides a simple and effective solution for long sequence layout tasks. Experiments conducted on ten representative PCB circuit benchmarks demonstrate that SRL reduces training time by 76.6% compared to traditional RL while exhibiting superior layout quality and enhanced complex problem solving capabilities in long sequence layout tasks.</p>

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SRL: A segmented reinforcement learning framework for long sequence layout decisions

  • Jie Yang,
  • Jian Chen,
  • Jinjin Hai,
  • Kai Qiao,
  • Haoran Zhang,
  • Bin Yan

摘要

Automated schematic layout for printed circuit boards (PCBs) is a critical step for security applications such as hardware Trojan detection and intellectual property verification. To address the challenges of state action space explosion and low training efficiency in reinforcement learning (RL) for PCB layout, posed by long decision sequences, this paper proposes a Segmented Reinforcement Learning (SRL) framework. SRL decouples long decision chains into sequential independent segments. Within each segment, separate segment agents optimize local policies, reducing state action space complexity while significantly improving training efficiency. Furthermore, segment agents achieve global coordination through cascaded propagation of optimal states, allowing SRL to avoid complex policy synchronization, which provides a simple and effective solution for long sequence layout tasks. Experiments conducted on ten representative PCB circuit benchmarks demonstrate that SRL reduces training time by 76.6% compared to traditional RL while exhibiting superior layout quality and enhanced complex problem solving capabilities in long sequence layout tasks.