Optimal loop filter design of a DC immunity single-phase PLL based single delay operator

Most phase-locked loops (PLLs) available for single-phase applications have at least two delay operators, one for orthogonality and the other for disturbance rejection, such as the DC offset and harmonic filtering. Multi-delay operators complicate the PLL and increase its computational burden. Therefore, a new solution for grid synchronization with DC immunity in single-phase applications is introduced utilizing only a single delay operator. A deep insight into the derivation of the PLL’s small-signal model, main characteristics, stability analysis, and loop filter design are discussed in this paper. The main advantages of the proposed method are explained in terms of several performance indexes, such as settling time, steady-state error, and ripples in the estimated grid information. This paper also aims to provide optimal tuning and design guidelines for the loop filter from the large-signal model perspective, including nonlinearities, adopting a stochastic optimization method. The practical swarm optimization is nominated to locate the loop filter gains optimally offline. The results of the offline stochastic optimization are used to explicitly formulate an online PI-controller gains formula as a function of the delay factor. Simulation and experimental tests validate the proposed method with comparison to other methods.