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<p>The phase-locked loop (PLL), conceived in 1932 by H. Bellescize, has been the basic electronic component in the development of communication technology from the early analog radio receptors to modern digital civil and military facilities. Traditionally, the analysis is conducted by modeling the dynamical behavior of phase and frequency errors, hence following a phase reduction approach which has the advantage of enabling bifurcation analyses related to phase. However, two main shortcomings are the fact that filtering is assumed ideal and it is not amenable to taking signal noise into account. One of the main goals of the present work is to investigate the performance of a PLL node under the effect of noise in the context of non-ideal filtering. This is accomplished using a full state space, which is complementary to the non-reductionist, model. Results show that by simulating the PLL node in a more realistic way a number of design-relevant aspects can now be investigated numerically.</p>

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Phase-Locked Loops in Non-Ideal Filtering and Noisy Scenarios

  • 期刊论文

  • 发表日期：

    2025年11月27日

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  • José Roberto C. Piqueira,
  • Felipe de Brito Freitas,
  • Luis Antonio Aguirre

摘要

The phase-locked loop (PLL), conceived in 1932 by H. Bellescize, has been the basic electronic component in the development of communication technology from the early analog radio receptors to modern digital civil and military facilities. Traditionally, the analysis is conducted by modeling the dynamical behavior of phase and frequency errors, hence following a phase reduction approach which has the advantage of enabling bifurcation analyses related to phase. However, two main shortcomings are the fact that filtering is assumed ideal and it is not amenable to taking signal noise into account. One of the main goals of the present work is to investigate the performance of a PLL node under the effect of noise in the context of non-ideal filtering. This is accomplished using a full state space, which is complementary to the non-reductionist, model. Results show that by simulating the PLL node in a more realistic way a number of design-relevant aspects can now be investigated numerically.