<p>The objective of this article is to design a simple step-by-step proportional integral (PI) damping controller (SS-PIDC) to damp out all low frequency oscillations to maintain power system network in stable manner under different failures and loss of input signals. The SS-PIDC is designed with the help of low frequency oscillations of a given network. To implement this SS-PIDC, the most dominating generators in low frequency oscillations are to be determined. The participation factors can be used to determine the most participating generators in each oscillation mode. After that rank all the generators in descending order from highest participating to lowest participating generator. Then, the conventional transfer function-based approach can be used to determine the required gains of this SS-PIDC. As per our goal, starts with implementing this SS-PIDC with the highest participating generator and so on. The effectiveness of this SS-PIDC can be verified by taking well-known IEEE-68 bus test system considering different system failures and loss of input signals of any PI controller. In addition, the performance of the proposed controller is compared with different existing controllers and the results and observations are illustrated.</p>

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Low Frequency Oscillations-Based Step-by-Step PI Damping Controller Design Resilient to Different Failures and Loss of Input Signals

  • Nagasekhara Reddy Naguru

摘要

The objective of this article is to design a simple step-by-step proportional integral (PI) damping controller (SS-PIDC) to damp out all low frequency oscillations to maintain power system network in stable manner under different failures and loss of input signals. The SS-PIDC is designed with the help of low frequency oscillations of a given network. To implement this SS-PIDC, the most dominating generators in low frequency oscillations are to be determined. The participation factors can be used to determine the most participating generators in each oscillation mode. After that rank all the generators in descending order from highest participating to lowest participating generator. Then, the conventional transfer function-based approach can be used to determine the required gains of this SS-PIDC. As per our goal, starts with implementing this SS-PIDC with the highest participating generator and so on. The effectiveness of this SS-PIDC can be verified by taking well-known IEEE-68 bus test system considering different system failures and loss of input signals of any PI controller. In addition, the performance of the proposed controller is compared with different existing controllers and the results and observations are illustrated.