Performance optimization of MFIS nanowire FeFET using silicon/InAs materials through TCAD simulation
摘要
The nanowire gate-all-around (GAA) MOSFET is recognised as a key architecture for future technology nodes due to its strong electrostatic control and enhanced gate-to-channel coupling. In this work, the performance of Si and InAs nanowire ferroelectric FETs (FeFETs) is investigated through TCAD simulations. Both devices exhibit their steepest subthreshold slope at a gate length of 90 nm with an average OFF-state current (IOFF) of 10−10 A/µm. Comparative analysis reveals that the Si nanowire FeFET exhibits a superior ION–IOFF ratio compared to its InAs counterpart, making it more suitable for low-power operations. Device metrics, including ON-state current (ION), threshold voltage (VTH), ION/IOFF ratio, and transconductance, are examined for gate lengths ranging from 22 to 90 nm. These findings offer valuable insights into the design of nanowire FeFETs for next-generation, energy-efficient applications.