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<p>This work investigates a Gate-All-Around Field-Effect Transistor (GAA-FET) architecture employing an underlap configuration, with Gallium Arsenide (GaAs) as the substrate material and silicon dioxide (SiO<sub>2</sub>) as the gate dielectric. The device is designed at the 22&#xa0;nm technology node, where the introduction of underlap regions—intentional spacing between the gate and source/drain contacts offers refined control over short-channel behavior and electrostatic integrity. The proposed GaAs underlap GAA-FET structure introduces an optimized 2.5&#xa0;nm underlap region validated through calibrated TCAD modeling, achieving improved short-channel control and switching efficiency compared to prior works. GaAs is selected for its high electron mobility, which enhances channel transport characteristics compared to conventional silicon-based implementations. Device modeling and electrical analysis are performed using Technology Computer-Aided Design (TCAD) tools to evaluate the impact of the underlap geometry on key performance indicators. Critical parameters, including <i>V</i><sub>th</sub>, drive current, leakage current, ON/OFF current ratio, subthreshold slope, and Drain-Induced Barrier Lowering (DIBL), are systematically analyzed. The role of fringing fields and parasitic capacitances induced by the underlap layout is also examined for their influence on switching behavior and device scaling. Simulation outcomes confirm that the proposed GaAs-based underlap GAA-FET structure offers improved electrostatic control, reduced leakage, and enhanced switching performance, positioning it as a strong candidate for future ultra-scaled, energy-efficient semiconductor technologies.</p>

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Performance of underlap GAA-FET using GaAs substrate and SiO2 gate oxide

  • 期刊论文

  • 发表日期：

    2025年12月3日

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  • P. Harikrishnan,
  • B. Mohan,
  • K. Rajesh,
  • R. Santhana Krishnan

摘要

This work investigates a Gate-All-Around Field-Effect Transistor (GAA-FET) architecture employing an underlap configuration, with Gallium Arsenide (GaAs) as the substrate material and silicon dioxide (SiO2) as the gate dielectric. The device is designed at the 22 nm technology node, where the introduction of underlap regions—intentional spacing between the gate and source/drain contacts offers refined control over short-channel behavior and electrostatic integrity. The proposed GaAs underlap GAA-FET structure introduces an optimized 2.5 nm underlap region validated through calibrated TCAD modeling, achieving improved short-channel control and switching efficiency compared to prior works. GaAs is selected for its high electron mobility, which enhances channel transport characteristics compared to conventional silicon-based implementations. Device modeling and electrical analysis are performed using Technology Computer-Aided Design (TCAD) tools to evaluate the impact of the underlap geometry on key performance indicators. Critical parameters, including Vth, drive current, leakage current, ON/OFF current ratio, subthreshold slope, and Drain-Induced Barrier Lowering (DIBL), are systematically analyzed. The role of fringing fields and parasitic capacitances induced by the underlap layout is also examined for their influence on switching behavior and device scaling. Simulation outcomes confirm that the proposed GaAs-based underlap GAA-FET structure offers improved electrostatic control, reduced leakage, and enhanced switching performance, positioning it as a strong candidate for future ultra-scaled, energy-efficient semiconductor technologies.