<p>This paper investigates deep learning as a possible alternative of numerical technology computer-aided design (TCAD) device simulation to introspect device performance of FinFETs (fin field-effect transistors). TCAD simulator is used here to analyze performance of a nanoscale junctionless FinFET device with a set of input parameters and its corresponding output parameters. The dataset is generated by varying Channel length, Fin width, and Spacer length of the device, and is then used to train the deep neural network model. As the dataset is comparatively small, 4 hidden layers are included while creating the deep neural network model. In the output, figure of merits (FoMs) of the device, such as threshold voltage (<i>V</i><sub>th</sub> in Volt), subthreshold slope (SS in mV/dec), and drain-induced barrier lowering (DIBL in mV/V), are considered separately. Output obtained using this model is compared with the results generated through TCAD simulation. Performance of the deep neural network model is evaluated by calculating coefficient of determination (<i>R</i><sup>2</sup>), mean absolute error (MAE), and root-mean-squared error (RMSE) and are found to be quite satisfactory. This research shows that the deep neural network model predicts figure of merits (FoMs) more efficiently, offering a compact model that requires less computing resource than TCAD simulation methods. This model is expected to be helpful for predicting fast and accurate device parameter for future technology nodes.</p>

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Performance evaluation of junctionless accumulation-mode FinFET using TCAD-enabled deep learning approach

  • Rachita Ghoshhajra,
  • Kalyan Biswas,
  • Mahamuda Sultana,
  • Angsuman Sarkar

摘要

This paper investigates deep learning as a possible alternative of numerical technology computer-aided design (TCAD) device simulation to introspect device performance of FinFETs (fin field-effect transistors). TCAD simulator is used here to analyze performance of a nanoscale junctionless FinFET device with a set of input parameters and its corresponding output parameters. The dataset is generated by varying Channel length, Fin width, and Spacer length of the device, and is then used to train the deep neural network model. As the dataset is comparatively small, 4 hidden layers are included while creating the deep neural network model. In the output, figure of merits (FoMs) of the device, such as threshold voltage (Vth in Volt), subthreshold slope (SS in mV/dec), and drain-induced barrier lowering (DIBL in mV/V), are considered separately. Output obtained using this model is compared with the results generated through TCAD simulation. Performance of the deep neural network model is evaluated by calculating coefficient of determination (R2), mean absolute error (MAE), and root-mean-squared error (RMSE) and are found to be quite satisfactory. This research shows that the deep neural network model predicts figure of merits (FoMs) more efficiently, offering a compact model that requires less computing resource than TCAD simulation methods. This model is expected to be helpful for predicting fast and accurate device parameter for future technology nodes.