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<p>Amorphous metal–oxide–semiconductor (MOS)-based thin-film transistors (TFTs) are gaining attention because of their favorable electrical performance and better operational stability than conventional amorphous silicon semiconductors. This study investigates the impact of the annealing temperature and multilayered structures on the performance and stability of indium–tin–zinc-oxide (ITZO) TFTs. ITZO semiconductors are fabricated under annealing temperatures of 350, 400, and 450&#xa0;°C to improve the quality of metal–oxide–metal (M–O–M) bonding networks and reduce defect states. Single-, bi-, and tri-layer film configurations are used to optimize the device’s performance and stability. TFTs fabricated at 400&#xa0;°C with a bi-layer coating show superior device performance and operational stability owing to superior M–O–M bonding networks and reduced charge-trapping characteristics compared to other cases. These results emphasize the importance of annealing temperature and layer thickness in achieving a high mobility, low threshold voltage, and device stability for next-generation display technologies.</p>

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Performance enhancement in solution-processed indium–tin–zinc-oxide thin-film transistors through annealing temperature modulation and multilayer stacking

  • 期刊论文

  • 发表日期：

    2025年7月15日

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  • Narendra Naik Mude,
  • Akash Bharat More,
  • Yu-Jung Cha,
  • Sung-Woon Cho

摘要

Amorphous metal–oxide–semiconductor (MOS)-based thin-film transistors (TFTs) are gaining attention because of their favorable electrical performance and better operational stability than conventional amorphous silicon semiconductors. This study investigates the impact of the annealing temperature and multilayered structures on the performance and stability of indium–tin–zinc-oxide (ITZO) TFTs. ITZO semiconductors are fabricated under annealing temperatures of 350, 400, and 450 °C to improve the quality of metal–oxide–metal (M–O–M) bonding networks and reduce defect states. Single-, bi-, and tri-layer film configurations are used to optimize the device’s performance and stability. TFTs fabricated at 400 °C with a bi-layer coating show superior device performance and operational stability owing to superior M–O–M bonding networks and reduced charge-trapping characteristics compared to other cases. These results emphasize the importance of annealing temperature and layer thickness in achieving a high mobility, low threshold voltage, and device stability for next-generation display technologies.