TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications

In this study, we propose a ferroelectric FET (FeFET) structure termed dual ferroelectric recessed channel FeFET (DF-RFeFET), employing metal–ferroelectric (FE)–metal–FE–metal–SiO₂ interlayer (IL)–silicon (MFMFMIS) structures. The DF-RFeFET is aimed at enhancing the memory window (MW) for high-performance memory applications. TCAD simulations with calibrated FE parameters and device models reveal that the DF-RFeFET can achieve a larger MW thanks to the enhanced geometric advantage to offer a strong and localized electric field at the inner ferroelectrics near the gate metal’s corner. Moreover, design guidelines for the DF-RFeFET are suggested, including adjusting the inner and outer ferroelectric layers' thickness ratio and the recessed channel depth. The effects of introducing a relatively low-k oxide intermediate layer between dual ferroelectric layers and high-k gate stacks of IL on the MW have also been investigated. Through structural optimization, the DF-RFeFET demonstrated a record MW value of 5.5 V among the previously reported Si FeFETs.