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<p>Efficient memory management remains a critical bottleneck in modern high-performance and multi-core computing systems. Traditional page replacement algorithms often fall short in addressing the divergent performance characteristics of RAM-to-HDD and RAM-to-SSD architectures, while also lacking adaptability to parallel memory access patterns in multi-core environments. This paper introduces TOPPER, a novel, hardware-aware page replacement algorithm designed to maximize success rate and minimize page faults, page access latency, energy consumption, and thermal dissipation. TOPPER leverages concurrent memory request patterns across processor cores to simulate partial future knowledge, enabling near-optimal page eviction decisions. The algorithm is benchmarked against classical (FIFO, LRU, LFU) and a range of advanced page replacement algorithms under four distinct use cases involving quad-core and octa-core configurations with varying memory frame sizes. Experimental evaluations demonstrate that TOPPER() consistently achieves higher success rates (up to 70%) while reducing page access time by a significant margin in both RAM-to-HDD and RAM-to-SSD scenarios. Additionally, it exhibits the lowest energy consumption and heat generation across all test cases. These results establish TOPPER() as a robust and scalable solution for next-generation memory systems operating under diverse hardware constraints and access workloads.</p>

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An Optimal Primary-to-Secondary Memory Page Replacement Algorithm for Multi-core Systems

  • 期刊论文

  • 发表日期：

    2026年6月14日

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  • Amar Ranjan Dash,
  • Chiranjib Mohapatra,
  • Baishnobi Dash,
  • Allu Saiswari,
  • Soumyamadhuri Nayak

摘要

Efficient memory management remains a critical bottleneck in modern high-performance and multi-core computing systems. Traditional page replacement algorithms often fall short in addressing the divergent performance characteristics of RAM-to-HDD and RAM-to-SSD architectures, while also lacking adaptability to parallel memory access patterns in multi-core environments. This paper introduces TOPPER, a novel, hardware-aware page replacement algorithm designed to maximize success rate and minimize page faults, page access latency, energy consumption, and thermal dissipation. TOPPER leverages concurrent memory request patterns across processor cores to simulate partial future knowledge, enabling near-optimal page eviction decisions. The algorithm is benchmarked against classical (FIFO, LRU, LFU) and a range of advanced page replacement algorithms under four distinct use cases involving quad-core and octa-core configurations with varying memory frame sizes. Experimental evaluations demonstrate that TOPPER() consistently achieves higher success rates (up to 70%) while reducing page access time by a significant margin in both RAM-to-HDD and RAM-to-SSD scenarios. Additionally, it exhibits the lowest energy consumption and heat generation across all test cases. These results establish TOPPER() as a robust and scalable solution for next-generation memory systems operating under diverse hardware constraints and access workloads.