Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology

With progress in the design of phase locked loop (PLL) circuit, critical parameters like, power dissipation, phase noise, and area, has had to be considered within the analysis. The key aspect of effective PLL design is the lock-in time, which presents a major challenge in the PLL usage in high-speed communication systems. As the PLLs are gradually being used for synchronization, clock synthesis, and reducing the jitter in wireless communications, due to increment in the circuit operation rate, there is an immediate need to design PLL circuits with fast locking capacity. In this article, an efficient PLL, employing current starved voltage controlled oscillator is designed to maintain linearity of its gain, using the Cadence Virtuoso tool, which is then simulated using the Spectre tool. Since the PLLs are extensively implemented over high frequency ranges due to incurring less time to lock frequency, the designed PLL’s lock time is set to 300 ns. Further, the designed PLL features a 3.09–3.2 GHz tuning range, a 5.2 GHz central frequency, small phase noise of − 71.51 dBc/Hz at 1000 kHz, along with 264 ps jitter. In addition, the proposed PLL dissipates a power of 50.8 μW, for 1 V supply. Extensive simulation results demonstrate that the proposed sub module architecture of the proposed PLL system performs better compared to the existing designs with respect to power consumption, operating frequency, phase noise, and jitter.