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<p>A multiplexer is a fundamental digital circuit that selects one input from several and routes it to the output based on control signals. In SFQ (Single Flux Quantum) logic, multiplexers play a crucial role in achieving high-speed and low-power signal routing. This paper presents the design of a 7:1 multiplexer using Single Flux Quantum (SFQ) logic. The proposed multiplexer is implemented using three select lines, with logic gates employed to decode the select signals. Two design approaches are explored: the first utilizes direct logic gate-based detection of select signals, and the second constructs the 7:1 multiplexer by cascading existing 3:1 and 4:1 SFQ multiplexer designs. Existing implementations of 7:1 multiplexers using cascaded 2:1 multiplexers require a larger number of select lines, which in turn leads to an increased number of splitters, confluence buffers, and Josephson junctions, resulting in higher power consumption. To address this, the proposed methods—Cascading 3:1 and 4:1 multiplexer and the Logic Gate-Based Select Detection (LGSD) method—aim to minimize the number of splitters, confluence buffers, and Josephson junctions, thereby improving power and area efficiency.</p>

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Hardware-Efficient 7:1 Multiplexer Design Using Cascaded Multiplexers and Logic Gate Methods

  • 期刊论文

  • 发表日期：

    2026年8月3日

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  • K. Sarangam,
  • Dharani Kumar Chowdary Mirappalli,
  • Gogineni Rajesh Chandra,
  • Vuppuloori Ravi Sekhara Reddy

摘要

A multiplexer is a fundamental digital circuit that selects one input from several and routes it to the output based on control signals. In SFQ (Single Flux Quantum) logic, multiplexers play a crucial role in achieving high-speed and low-power signal routing. This paper presents the design of a 7:1 multiplexer using Single Flux Quantum (SFQ) logic. The proposed multiplexer is implemented using three select lines, with logic gates employed to decode the select signals. Two design approaches are explored: the first utilizes direct logic gate-based detection of select signals, and the second constructs the 7:1 multiplexer by cascading existing 3:1 and 4:1 SFQ multiplexer designs. Existing implementations of 7:1 multiplexers using cascaded 2:1 multiplexers require a larger number of select lines, which in turn leads to an increased number of splitters, confluence buffers, and Josephson junctions, resulting in higher power consumption. To address this, the proposed methods—Cascading 3:1 and 4:1 multiplexer and the Logic Gate-Based Select Detection (LGSD) method—aim to minimize the number of splitters, confluence buffers, and Josephson junctions, thereby improving power and area efficiency.