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<p>Approximation is the breakthrough in the power, delay and area trade off problem. In Approximation, accuracy is traded off for reduction in hardware cost. Digital Signal Processing applications can tolerate imprecise computation. These applications can use approximate arithmetic circuits to achieve reduced hardware cost. In this work, authors develop two new 4:2 compressor designs, C4:2e0 and C4:2e2, by applying traditional Karnaugh map (K-map) simplification with purposefully inserted logic approximations. The K-map technique itself is not original in this study; rather, it is novel in (i) the particular approximation choices chosen during simplification, (ii) the ensuing error traits associated with the two designs, and (iii) their hardware efficiency trade-offs when implemented in 8 × 8 Dadda multipliers. it provide a thorough quantitative assessment of hardware metrics (area, power, delay) and accuracy (ER, MED, MRED, NMED) that shows the usefulness of these designs in error-tolerant computing domains. The designed compressors are synthesized using TSMC’s 90&#xa0;nm digital library. Experiments reveal that the proposed compressors have the lowest delay when analysed against the latest 4:2 compressors in literature.</p>

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Hardware Optimization for DSP: Design of Approximate 4:2 Compressors in Multipliers

  • 期刊论文

  • 发表日期：

    2026年6月19日

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  • R. Naveenkumar,
  • S. Isaac Daniel,
  • S. Sridevi Sathyapriya,
  • N. M. Sivamangai

摘要

Approximation is the breakthrough in the power, delay and area trade off problem. In Approximation, accuracy is traded off for reduction in hardware cost. Digital Signal Processing applications can tolerate imprecise computation. These applications can use approximate arithmetic circuits to achieve reduced hardware cost. In this work, authors develop two new 4:2 compressor designs, C4:2e0 and C4:2e2, by applying traditional Karnaugh map (K-map) simplification with purposefully inserted logic approximations. The K-map technique itself is not original in this study; rather, it is novel in (i) the particular approximation choices chosen during simplification, (ii) the ensuing error traits associated with the two designs, and (iii) their hardware efficiency trade-offs when implemented in 8 × 8 Dadda multipliers. it provide a thorough quantitative assessment of hardware metrics (area, power, delay) and accuracy (ER, MED, MRED, NMED) that shows the usefulness of these designs in error-tolerant computing domains. The designed compressors are synthesized using TSMC’s 90 nm digital library. Experiments reveal that the proposed compressors have the lowest delay when analysed against the latest 4:2 compressors in literature.