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<p>Reversible Logic (RL) has drawn significant attention in the recent research offering benefits of reduced power consumption, no information loss and ensuring a fault tolerant system. These benefits find relevance to quantum computing- the technology of the future and expected to offer fast, computationally efficient system designs. With the objective to optimize the reversible gate implementation of classical arithmetic operations, the proposed work explores the RL gates for efficient design of a Full adder. Full addition is a primitive operation used in complex computationally intensive system designs varying from cryptographic algorithms to signal processing applications. This work explores a novel reversible logic-based implementation of Full adder circuit and evaluates the proposed design in terms of power, garbage outputs, ancilla inputs and quantum cost. The optimized design has been implemented as 32-bit efficient Reversible Full adder using Artix 7 Xilinx XC7a35tcp236-1. The results obtained shows efficient design with quantum cost of 15, 1 ancilla inputs, Garbage outputs of 2 and gate count of 6. The results obtained are best when compared to the existing designs in literature evaluated using hardware implementation specially the only design in 4 × 4 configuration with full analysis of Quantum cots, gate count, power and delay. Also, except standard Peres-Peres Full adder implementation this is first gate which is fully bijective and recovering all the inputs from outputs.</p>

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Hardware Implementation of an Efficient 32-bit Reversible Full Adder and its Analysis for Quantum applications

  • 期刊论文

  • 发表日期：

    2026年6月27日

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  • Gaganpreet Kaur,
  • Khushpreet Singh,
  • Rudraa Dadhich,
  • Tanish Sadana,
  • Nishant Mittal,
  • Vanshika Garg,
  • Ishaana Ali

摘要

Reversible Logic (RL) has drawn significant attention in the recent research offering benefits of reduced power consumption, no information loss and ensuring a fault tolerant system. These benefits find relevance to quantum computing- the technology of the future and expected to offer fast, computationally efficient system designs. With the objective to optimize the reversible gate implementation of classical arithmetic operations, the proposed work explores the RL gates for efficient design of a Full adder. Full addition is a primitive operation used in complex computationally intensive system designs varying from cryptographic algorithms to signal processing applications. This work explores a novel reversible logic-based implementation of Full adder circuit and evaluates the proposed design in terms of power, garbage outputs, ancilla inputs and quantum cost. The optimized design has been implemented as 32-bit efficient Reversible Full adder using Artix 7 Xilinx XC7a35tcp236-1. The results obtained shows efficient design with quantum cost of 15, 1 ancilla inputs, Garbage outputs of 2 and gate count of 6. The results obtained are best when compared to the existing designs in literature evaluated using hardware implementation specially the only design in 4 × 4 configuration with full analysis of Quantum cots, gate count, power and delay. Also, except standard Peres-Peres Full adder implementation this is first gate which is fully bijective and recovering all the inputs from outputs.