Vertical Tunnel Field Effect Transistors (VTFETs) have emerged as promising candidates for next-generation ultra-low-power electronics due to their capability to achieve steep subthreshold swing and reduced leakage current beyond the limitations of conventional MOSFETs. In this work, a comprehensive performance investigation of three silicon-based dual-gate VTFET architectures, namely the basic HfO \(_2\) dielectric VTFET, Long Gate Long Dielectric (LGLD) VTFET, and Asymmetric Drain Long Gate Long Dielectric (AD-LGLD) VTFET, is presented using TCAD simulation. The impact of structural modifications on internal electrostatics, energy band distribution, electric field components, carrier generation, and tunneling behavior is systematically analyzed. Results demonstrate that the AD-LGLD VTFET significantly enhances the electric field concentration at the source-channel tunneling junction, leading to improved band-to-band tunneling efficiency while simultaneously suppressing drain-side ambipolar conduction. The proposed structure achieves an ON-current of \(7.3 \times 10^{-7}\) A, OFF-current of \(1.59 \times 10^{-15}\) A, subthreshold swing of 47 mV/dec, and an \(I_{\textrm{ON}}/I_{\textrm{OFF}}\) ratio of \(4.57 \times 10^{8}\) . Owing to its silicon-compatible material system, simple fabrication feasibility, and superior electrostatic control, the AD-LGLD VTFET is identified as a strong candidate for future energy-efficient integrated circuits.
