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<p>Wireless sensor networks are a relatively new class of networks that have recently attracted a lot of attention from academia and business. If there are enough redundant nodes available to keep the network functioning and connected in the event of node failures, the network's ability to self-organize makes it robust and fault-tolerant. The router, which plays a key role in organizing the data flow, is the brain of an on-chip network. The main components of the WSNs are the routers, which oversee sending messages and publishing-subscribe events between senders and receivers. A high level of parallelism and a fast on-chip router are both made possible by allowing routing functions for each input port and utilizing distributed arbiters. The research article focuses on the hardware chip design of mesh configured network on chip routers chip with embedding RSA cryptographic algorithm. The chip design is done in Xilinx ISE, simulated in Modelsim with different key sizes, and analyzed on Virtex-5 field programmable gate array. The performance of the network is evaluated using delay and power as the major indices with different key lengths and the design has proven the maximum frequency support of 347.00&#xa0;MHz.</p>

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Router Chip with RSA Embedded Security for Delay and Power Study in Sensory Data Communication

  • 期刊论文

  • 发表日期：

    2025年3月25日

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  • Prateek Agarwal,
  • Tanuj Kumar Garg,
  • Adesh Kumar

摘要

Wireless sensor networks are a relatively new class of networks that have recently attracted a lot of attention from academia and business. If there are enough redundant nodes available to keep the network functioning and connected in the event of node failures, the network's ability to self-organize makes it robust and fault-tolerant. The router, which plays a key role in organizing the data flow, is the brain of an on-chip network. The main components of the WSNs are the routers, which oversee sending messages and publishing-subscribe events between senders and receivers. A high level of parallelism and a fast on-chip router are both made possible by allowing routing functions for each input port and utilizing distributed arbiters. The research article focuses on the hardware chip design of mesh configured network on chip routers chip with embedding RSA cryptographic algorithm. The chip design is done in Xilinx ISE, simulated in Modelsim with different key sizes, and analyzed on Virtex-5 field programmable gate array. The performance of the network is evaluated using delay and power as the major indices with different key lengths and the design has proven the maximum frequency support of 347.00 MHz.