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<p>The role of multipliers is crucial in arithmetic operations. High-speed multiplier design is the major prerequisite for the fastest computation. Vedic multiplier (VM) is unique among multiplier architectures because of their innate speed and efficiency. This paper presents the implementation of an 8-bit VM using the hybrid adder (HyA) on the field-programmable gate array (FPGA) device. The HyA is the integration of the ripple carry adder (RCA) and carry look-ahead adder (CLA). The path delay and gate area are briefly discussed. The multiplier has been implemented on the Kintex-7 FPGA device using Xilinx Vivado 2024.2.The synthesis report suggested the presented 8-bit VM using HyA improved the area-delay product (ADP) by about 14.76% and the power-delay product (PDP) by about 10.69% compared to the recent multiplier.</p>

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Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder

  • 期刊论文

  • 发表日期：

    2025年12月3日

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  • Debarshi Datta,
  • Mrinal Kanti Naskar

摘要

The role of multipliers is crucial in arithmetic operations. High-speed multiplier design is the major prerequisite for the fastest computation. Vedic multiplier (VM) is unique among multiplier architectures because of their innate speed and efficiency. This paper presents the implementation of an 8-bit VM using the hybrid adder (HyA) on the field-programmable gate array (FPGA) device. The HyA is the integration of the ripple carry adder (RCA) and carry look-ahead adder (CLA). The path delay and gate area are briefly discussed. The multiplier has been implemented on the Kintex-7 FPGA device using Xilinx Vivado 2024.2.The synthesis report suggested the presented 8-bit VM using HyA improved the area-delay product (ADP) by about 14.76% and the power-delay product (PDP) by about 10.69% compared to the recent multiplier.