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<p>Recurrent neural networks (RNNs) are capable of learning data sequences and retaining memories. It can be challenging to parallelize all RNN computations because of the recurrent nature of the network. The research letter emphasizes the design and simulation of a fully RNN chip that processes 64 neurons in two hidden layers based on a finite state machine (FSM) design and synthesis on different field programmable gate array (FPGA) hardware. The chip design performance is verified on different FPGAs such as Virtex-7, Virtex-5, Virtex-4, Spartan-6, and Spartan-3E in Xilinx ISE 14.7 software and simulated in Modelsim 10.0 software for functional and logic verification. The analysis of RNN hardware chips on different FPGA assessed the ideal solution on Virtex-7 FPGA in terms of maximum frequency support of 425.00&#xa0;MHz, minimal combinational latency of 4.03ns, and power consumption of 6.00&#xa0;W, which is optimal in comparison with other FPGAs.</p>

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Recurrent Neural Network Chip for Fast Switching and Minimum Delay on Different Hardware

  • 期刊论文

  • 发表日期：

    2025年7月3日

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  • Akash Goel,
  • Amit Kumar Goel,
  • Adesh Kumar

摘要

Recurrent neural networks (RNNs) are capable of learning data sequences and retaining memories. It can be challenging to parallelize all RNN computations because of the recurrent nature of the network. The research letter emphasizes the design and simulation of a fully RNN chip that processes 64 neurons in two hidden layers based on a finite state machine (FSM) design and synthesis on different field programmable gate array (FPGA) hardware. The chip design performance is verified on different FPGAs such as Virtex-7, Virtex-5, Virtex-4, Spartan-6, and Spartan-3E in Xilinx ISE 14.7 software and simulated in Modelsim 10.0 software for functional and logic verification. The analysis of RNN hardware chips on different FPGA assessed the ideal solution on Virtex-7 FPGA in terms of maximum frequency support of 425.00 MHz, minimal combinational latency of 4.03ns, and power consumption of 6.00 W, which is optimal in comparison with other FPGAs.