Hardware Implementation of Digital Down Converter for W-CDMA System

This paper implements a field-programmable gate array (FPGA)-based digital down converter (DDC), reducing the sampling rate from 160MSps to 10MSps. The suggested DDC consists of a polyphase cascaded integrator comb (CIC) and a low-pass polyphase finite impulse response (FIR) filter. The mathematical expressions of the polyphase CIC filter are briefly described. The programmable decimation factor in each filter can improve the flexibility of the design. The filter coefficients are synthesized into the fixed-point format to meet the desired stopband and passband attenuation characteristics. The design is implemented on the Kintex-7 FPGA device. Comparison results indicate that the presented DDC uses less resources by about 14.67% and power consumption by about 12.80%. Functional verification is also established to meet the desired specifications.