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<p>To enhance the memory characteristics of the 2-transistor 0-capacitor (2T0C) DRAM cell, the double-layer (DL) InGaZnO channel was strategically introduced and the active geometry was optimally modulated. The DL channel, fabricated by modulating the oxygen partial pressure during RF sputtering, forms a heterojunction interface that introduces an additional conduction path, thereby significantly enhancing the device performance of the transistor. In memory operations, 2T0C DRAM cell employing the DL configuration exhibited more than twice the write speed, reaching a storage node voltage (V<sub>SN</sub>) of 0.8&#xa0;V within 4&#xa0;µs, compared to 10&#xa0;µs for single-layer (SL) counterpart under identical charging conditions. Additionally, the optimal determination of the active geometry in transistors has been demonstrated to enhance charge storage efficiency and minimize V<sub>SN</sub> degradation. As a consequence of the enhanced positive-bias temperature stress stability, the DL device exhibited a data retention time of 44.3&#xa0;s at 80&#xa0;°C, which is approximately four times longer than that of the SL counterpart (11.5&#xa0;s) with identical geometry. These findings confirm that the combined implementation of a DL IGZO channel and optimized device geometry provides an effective strategy for enhancing both the performance and reliability of 2T0C DRAM cell architectures.</p> Graphic Abstract <p></p>

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Improvement in Memory Operation of 2T0C DRAM Cells via Double-Layered InGaZnO Active Channel and Geometry Modulation

  • 期刊论文

  • 发表日期：

    2025年6月26日

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  • Sang Han Ko,
  • Sung-Min Yoon

摘要

To enhance the memory characteristics of the 2-transistor 0-capacitor (2T0C) DRAM cell, the double-layer (DL) InGaZnO channel was strategically introduced and the active geometry was optimally modulated. The DL channel, fabricated by modulating the oxygen partial pressure during RF sputtering, forms a heterojunction interface that introduces an additional conduction path, thereby significantly enhancing the device performance of the transistor. In memory operations, 2T0C DRAM cell employing the DL configuration exhibited more than twice the write speed, reaching a storage node voltage (VSN) of 0.8 V within 4 µs, compared to 10 µs for single-layer (SL) counterpart under identical charging conditions. Additionally, the optimal determination of the active geometry in transistors has been demonstrated to enhance charge storage efficiency and minimize VSN degradation. As a consequence of the enhanced positive-bias temperature stress stability, the DL device exhibited a data retention time of 44.3 s at 80 °C, which is approximately four times longer than that of the SL counterpart (11.5 s) with identical geometry. These findings confirm that the combined implementation of a DL IGZO channel and optimized device geometry provides an effective strategy for enhancing both the performance and reliability of 2T0C DRAM cell architectures.

Graphic Abstract