Scholarlink

<p>Providing a secure hardware infrastructure is a key challenge in implementing secure cryptographic algorithms. Even a robust algorithm with suitable key lengths is not effective against differential power analysis (DPA) attacks and can cause the cryptographic key to be discovered. Today, credit cards and electronic identification cards, due to the greater scope of applications are subjected to differential power analysis attacks. As a result, a good design can help maintain the confidentiality of information. Providing a design method that balances the power consumption of the outputs and inputs of chips results a DPA secure designs. Moreover, reducing power consumption by recovering the charge stored in nodes makes power tracing more difficult. On the other hand, designing a uniform pattern in the transistor surface shape for all logic gates will make them resilient against advanced imaging techniques. In this paper a DPA resilient design method is proposed which is also robust against some other attacks such as timing attacks and advanced image processing techniques. The presented designs are simulated and compared with the state-of-the-art designs using Synopsis HSPICE with 22&#xa0;nm technology node. Simulation results show that the proposed method achieves the lowest and most balanced power consumption compared to the other designs.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

BLCD: a balanced and low-power cell design family for secure applications

  • 期刊论文

  • 发表日期：

    2026年5月2日

查看全文
  • Alireza Shirmohammadi,
  • Hamid Reza Naji,
  • Fazel Sharifi

摘要

Providing a secure hardware infrastructure is a key challenge in implementing secure cryptographic algorithms. Even a robust algorithm with suitable key lengths is not effective against differential power analysis (DPA) attacks and can cause the cryptographic key to be discovered. Today, credit cards and electronic identification cards, due to the greater scope of applications are subjected to differential power analysis attacks. As a result, a good design can help maintain the confidentiality of information. Providing a design method that balances the power consumption of the outputs and inputs of chips results a DPA secure designs. Moreover, reducing power consumption by recovering the charge stored in nodes makes power tracing more difficult. On the other hand, designing a uniform pattern in the transistor surface shape for all logic gates will make them resilient against advanced imaging techniques. In this paper a DPA resilient design method is proposed which is also robust against some other attacks such as timing attacks and advanced image processing techniques. The presented designs are simulated and compared with the state-of-the-art designs using Synopsis HSPICE with 22 nm technology node. Simulation results show that the proposed method achieves the lowest and most balanced power consumption compared to the other designs.