Utilizing layout effects for analog logic locking

While numerous obfuscation techniques are available for securing digital assets in the digital domain, there has been a notable lack of focus on protecting intellectual property (IP) in the analog domain. This is primarily due to the relatively smaller footprint of analog components within an integrated circuit (IC), with the majority of the surface dedicated to digital elements. However, despite their smaller nature, analog components are highly valuable IP and warrant effective protection. In this paper, we present a groundbreaking method for safeguarding analog IP by harnessing layout-based effects that are typically considered undesirable in IC design. Specifically, we exploit the impact of length of oxide diffusion and well proximity effect on transistors to fine-tune critical parameters such as transconductance ( \(g_{m}\) $g_m$ ) and threshold voltage ( \(V_{th}\) $V_{\mathit{th}}$ ). These parameters remain concealed behind key inputs, akin to the logic locking approach employed in digital ICs. Our research explores the application of layout-based effects in two commercial CMOS technologies, namely a 28 nm and a 65 nm node. To demonstrate the efficacy of our proposed technique, we implement it for locking an operational transconductance amplifier. Extensive simulations are performed, evaluating the obfuscation strength by applying a large number of key sets (over 50,000 and 300,000). The results exhibit a significant degradation in performance metrics, such as open-loop gain (up to 130 dB), phase margin (up to 50 \(^\circ \) ${}^{\circ }$ ), 3 dB bandwidth (approximately 2.5 MHz), and power consumption (around 1 mW) when incorrect keys are employed. Our findings highlight the advantages of our approach as well as the associated overhead.