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<p>This study aims to establish a comprehensive understanding of the performance differences between Forksheet (FS) and Nanosheet (NS) FETs at the 5-nm technology node through detailed TCAD simulations, with the academic objective of assessing their suitability for future high-performance and low-power logic applications. The primary goal is to analyze how structural modifications in FS FETs, particularly the integration of both nMOS and pMOS transistors within a single structure separated by a dielectric wall, influence device scalability, electrostatic control, and overall circuit efficiency. To achieve this, the investigation encompasses both DC and analog performance metrics, focusing on parameters such as ON-state current and subthreshold slope under identical device conditions. The study further examines the impact of FS FET width variation on electrical characteristics to identify optimal design trade-offs. Beyond the device level, circuit-level evaluations are conducted for inverter, NAND, and NOR configurations at multiple supply voltages (0.7, 0.5, and 0.3&#xa0;V) to understand the implications of FS architecture on logic circuit behavior. Simulation results indicate that FS FETs demonstrate superior ON-state current, improved subthreshold slope, and enhanced scalability compared to NS FETs. Furthermore, FS FET-based inverters maintain consistent voltage gain and static noise margin (SNM) across all supply voltages, confirming their robustness for low-power operation. The FS FET-based NAND and NOR gates also achieve approximately 90 and 30% higher speed, respectively, than their NS counterparts. These findings collectively fulfill the academic objectives of the study by confirming that FS FETs offer significant advantages in speed, energy efficiency, and electrostatic control, positioning them as a promising candidate for next-generation CMOS technology at advanced nodes.</p>

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Circuit-Level Analysis of Spacer Dielectrics in Forksheet FETs for High-Speed Digital Applications

  • 期刊论文

  • 发表日期：

    2026年6月3日

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  • K. Murali Chandra Babu,
  • Siddhali Gadiya,
  • Swaroop Kumar Macherla,
  • Ekta Goel

摘要

This study aims to establish a comprehensive understanding of the performance differences between Forksheet (FS) and Nanosheet (NS) FETs at the 5-nm technology node through detailed TCAD simulations, with the academic objective of assessing their suitability for future high-performance and low-power logic applications. The primary goal is to analyze how structural modifications in FS FETs, particularly the integration of both nMOS and pMOS transistors within a single structure separated by a dielectric wall, influence device scalability, electrostatic control, and overall circuit efficiency. To achieve this, the investigation encompasses both DC and analog performance metrics, focusing on parameters such as ON-state current and subthreshold slope under identical device conditions. The study further examines the impact of FS FET width variation on electrical characteristics to identify optimal design trade-offs. Beyond the device level, circuit-level evaluations are conducted for inverter, NAND, and NOR configurations at multiple supply voltages (0.7, 0.5, and 0.3 V) to understand the implications of FS architecture on logic circuit behavior. Simulation results indicate that FS FETs demonstrate superior ON-state current, improved subthreshold slope, and enhanced scalability compared to NS FETs. Furthermore, FS FET-based inverters maintain consistent voltage gain and static noise margin (SNM) across all supply voltages, confirming their robustness for low-power operation. The FS FET-based NAND and NOR gates also achieve approximately 90 and 30% higher speed, respectively, than their NS counterparts. These findings collectively fulfill the academic objectives of the study by confirming that FS FETs offer significant advantages in speed, energy efficiency, and electrostatic control, positioning them as a promising candidate for next-generation CMOS technology at advanced nodes.