Secure and efficient visual transmission is becoming increasingly important in industrial, medical, and defense applications. This study builds a fully pipelined AES-128 architecture on an Intel Cyclone V FPGA using Verilog HDL and Intel Quartus Prime. To confirm the concept, a 512 \(\times \) 512 grayscale image was encrypted and decoded. The system achieves a throughput of 10.385 Gbps at 176.43 MHz. Compared to current FPGA-based AES designs, the post-implementation design exhibits comparable performance with remarkable energy efficiency, with a total device power of 1.99 W and a core dynamic power of only 29.38 mW. A design-space study of pipeline depth highlights the trade-offs between throughput, latency, and power and shows how the architecture can be analytically modified for different application domains. The results show that, in addition to providing real-time performance, the proposed solution offers remarkable energy efficiency of 353.5 Gbps/W and throughput efficiency of 1.32 Mbps/ALM, making it suitable for embedded systems with limited resources.
