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<p>In-memory computing (IMC) has emerged as a promising paradigm for accelerating neural network operations by performing computation directly within memory. However, limited foundry support, high energy cost of on-chip learning, and endurance issues with emerging devices such as resistive RAM and floating-gate memories restrict their broader applicability in rapid artificial neural network (ANN) prototyping. In this context, this work proposes a mixed-signal analog computing approach for ANN synaptic operations, using a programmable conductive memory (G-RAM) in a differential crossbar array built with MOSFETs. Synaptic operations are performed using G-RAM-based analog voltage multipliers with a mixed-signal activation unit in the output layer. The architecture supports on-chip learning with self-trainable weights. Rigorous SPICE simulation has shown that it can achieve robust functionality in a 4-4-3-1 multilayer perceptron (MLP) for the XOR problem with precision of <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(94\%\)</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mn>94</mn> <mo>%</mo> </mrow> </math></EquationSource> </InlineEquation> and energy efficiency of 4.28 TOPS/J (Tera Operations per Second per Joule). Furthermore, a larger MLP with a 784-128-10 architecture for MNIST digit classification achieved a system accuracy of 92% using the differential crossbar architecture with discrete conductance states and sigmoid activation validating the scalability.</p>

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A Mixed-Signal VLSI Architecture Design for ANN Based on MOS-Conductance Memory

  • 期刊论文

  • 发表日期：

    2025年12月1日

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  • Anirban Ganguly,
  • Debanjana Datta Mitra,
  • Kingshuk Garai,
  • Ayan Banerjee

摘要

In-memory computing (IMC) has emerged as a promising paradigm for accelerating neural network operations by performing computation directly within memory. However, limited foundry support, high energy cost of on-chip learning, and endurance issues with emerging devices such as resistive RAM and floating-gate memories restrict their broader applicability in rapid artificial neural network (ANN) prototyping. In this context, this work proposes a mixed-signal analog computing approach for ANN synaptic operations, using a programmable conductive memory (G-RAM) in a differential crossbar array built with MOSFETs. Synaptic operations are performed using G-RAM-based analog voltage multipliers with a mixed-signal activation unit in the output layer. The architecture supports on-chip learning with self-trainable weights. Rigorous SPICE simulation has shown that it can achieve robust functionality in a 4-4-3-1 multilayer perceptron (MLP) for the XOR problem with precision of \(94\%\) 94 % and energy efficiency of 4.28 TOPS/J (Tera Operations per Second per Joule). Furthermore, a larger MLP with a 784-128-10 architecture for MNIST digit classification achieved a system accuracy of 92% using the differential crossbar architecture with discrete conductance states and sigmoid activation validating the scalability.