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<p>A new approximation of the exponential function is introduced, which supports a wide range of input and output values. The presented eighth-order modified pseudo-Taylor exponential approximation (MPTEA) is mathematically proven and implemented in both analog and digital domains. Strong inversion characteristics of metal–oxide–semiconductor field-effect transistors (MOSFETs) based on 90&#xa0;nm technology are employed to determine the authenticity of the analog implementation. A typical voltage-biased squarer circuit is used to implement the proposed eighth-order MPTEA within the input range of −&#xa0;10 ≤ × ≤ 10. The silicon area of the MPTEA is 553.984&#xa0;µm<sup>2</sup>, and the post-layout results for power and −&#xa0;3&#xa0;dB bandwidth are 455.74&#xa0;µW and 29.1&#xa0;MHz, respectively, showing discrepancies of 8.83% and 7.91% compared to the pre-layout simulations. The proposed MPTEA exhibits a wide output range of 173.3&#xa0;dB, with a corresponding error of ± 0.34&#xa0;dB. On the other hand, a Spartan3E field-programmable gate array (FPGA) is used for the digital verification of the presented MPTEA, and as an elegant technique, a clock-based MPTEA generator with variable accuracy is implemented, and the hardware features are extracted. In the digital domain, the presented unit precisely follows the exponential function. The implementation of the proposed MPTEA, in both analog (strong inversion) and digital (FPGA) domains, expresses distinct features that are applicable to control and computational systems, respectively.</p>

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A New Wide-Range Eighth-Order Exponential Approximation Implemented in Both Strong Inversion Regime and Field Programmable Gate Array

  • 期刊论文

  • 发表日期：

    2025年9月15日

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  • Saina Parvanehnezhad Shirazian,
  • Nabiollah Shiri

摘要

A new approximation of the exponential function is introduced, which supports a wide range of input and output values. The presented eighth-order modified pseudo-Taylor exponential approximation (MPTEA) is mathematically proven and implemented in both analog and digital domains. Strong inversion characteristics of metal–oxide–semiconductor field-effect transistors (MOSFETs) based on 90 nm technology are employed to determine the authenticity of the analog implementation. A typical voltage-biased squarer circuit is used to implement the proposed eighth-order MPTEA within the input range of − 10 ≤ × ≤ 10. The silicon area of the MPTEA is 553.984 µm2, and the post-layout results for power and − 3 dB bandwidth are 455.74 µW and 29.1 MHz, respectively, showing discrepancies of 8.83% and 7.91% compared to the pre-layout simulations. The proposed MPTEA exhibits a wide output range of 173.3 dB, with a corresponding error of ± 0.34 dB. On the other hand, a Spartan3E field-programmable gate array (FPGA) is used for the digital verification of the presented MPTEA, and as an elegant technique, a clock-based MPTEA generator with variable accuracy is implemented, and the hardware features are extracted. In the digital domain, the presented unit precisely follows the exponential function. The implementation of the proposed MPTEA, in both analog (strong inversion) and digital (FPGA) domains, expresses distinct features that are applicable to control and computational systems, respectively.