Impact of Interface Traps on Reliability in Negative Capacitance Source Pocket Double Gate TFET
摘要
The study investigates the reliability and performance of Negative Capacitance Source Pocket Double-Gate Tunnel Field-Effect Transistors (NC-SP-DGTFETs), focusing on the influence of interface trap charges (ITCs) at the Silicon–Silicon dioxide interface. Both positive and negative ITCs were analyzed to determine their impact on the DC and analog/RF performance of NC-SP-DGTFETs. The results indicate that variations in ITC concentrations have minimal impact on the device’s performance metrics, demonstrating that NC-SP-DGTFETs exhibit superior resilience to ITCs compared to other semiconductor devices, which often suffer significant performance degradation due to ITCs. Moreover, the study underscores the practical potential of NC-SP-DGTFETs by successfully designing a Common-Source amplifier with a gain of 3.4. This emphasizes the NC-SP-DGTFETs’ potential for use in advanced, high-speed, low-power integrated circuits. Their impressive performance across different conditions and resistance to ITCs position them as promising candidates for future electronics, particularly where reliability and energy efficiency are essential.