High-Efficient Gate Diffusion Input-Based Approximate Full Adders with Low-Transistors Preservation for Multiplier-Based Digital Filters

This research focuses on proposing extremely low area full adders (FAs) by leveraging approximate computing to sacrifice a certain degree of accuracy. Three novel approximate FAs are proposed, featuring transistor counts of 8, 4, and 2, and named Cell-1, Cell-2, and Cell-3, respectively. All three circuits exhibit four errors, but their error distribution is distinctive, and they utilize different gate-level structures compared to references. The gate diffusion input (GDI) gates varying mean relative error distances (MREDs). Cell-1 has an MRED of 0.3541, while Cell-2 and Cell-3 achieve a value of 0.3125. These circuits demonstrate notable performance by the GDI, dynamic threshold (DT), and the incorporation of carbon nanotube field-effect transistors (CNTFETs) to address threshold voltage drop challenges. Regarding power-delay product (PDP), the best circuits are Cell-2 and Cell-3. A 35.41% improvement is seen by Cell-3 compared to Cell-2 and a 6.89% lower energy gained by Cell-2 compared to the nearest competitor. Cell-2 demonstrates the best performance when embedded in the proposed multiplier. In practical applications of image addition and finite impulse response (FIR) filtering of an electrocardiogram (ECG), the FAs make efficient 10-bit ripple carry adders (RCAs).